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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
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rev.1.00, mar.12.2004, page 1 of 12 r1rp0416di series wide temperature range version 4m high speed sram (256-kword 16-bit) rej03c0110-0100z rev. 1.00 mar.12.2004 description the r1rp0416di series is a 4-mbit high speed static ram organized 256-k word 16-bit. it has realized high speed access time by employing cmos process (6-transistor memory cell) and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. it is packaged in 400-mil 44-pin plastic soj and 400-mil 44-pin plastic tsopii. features ? single 5.0 v supply: 5.0 v 10% ? access time: 12 ns (max) ? completely static memory ? no clock or timing strobe required ? equal access and cycle times ? directly ttl compatible ? all inputs and outputs ? operating current: 160 ma (max) ? ttl standby current: 40 ma (max) ? cmos standby current: 5 ma (max) ? center v cc and v ss type pin out ? temperature range: ? 40 to +85 c ordering information type no. access time package r1rp0416dge-2pi 12 ns 400-mil 44-pin plastic soj (44p0k) r1rp0416dsb-2pi 12 ns 400-mil 44-pin plastic tsopii (44p3w-h)
r1rp0416di series rev.1.00, mar.12.2004, page 2 of 12 pin arrangement a0 a1 a2 a3 a4 cs# i/o1 i/o2 i/o3 i/o4 v cc v ss i/o5 i/o6 i/o7 i/o8 we# a5 a6 a7 a8 a9 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a17 a16 a15 oe# ub# lb# i/o16 i/o15 i/o14 i/o13 v ss v cc i/o12 i/o11 i/o10 i/o9 nc a14 a13 a12 a11 a10 44-pin soj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a0 a1 a2 a3 a4 cs# i/o1 i/o2 i/o3 i/o4 v cc v ss i/o5 i/o6 i/o7 i/o8 we# a5 a6 a7 a8 a9 a17 a16 a15 oe# ub# lb# i/o16 i/o15 i/o14 i/o13 v ss v cc i/o12 i/o11 i/o10 i/o9 nc a14 a13 a12 a11 a10 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-pin tsop (top view) pin description pin name function a0 to a17 address input i/o1 to i/o16 data input/output cs# chip select oe# output enable we# write enable ub# upper byte select lb# lower byte select v cc power supply v ss ground nc no connection
r1rp0416di series rev.1.00, mar.12.2004, page 3 of 12 block diagram 1024-row 32-column 8-block 16-bit (4,194,304 bits) cs v cc v ss a8 a9 a17 a15 a16 a0 a2 a4 column i/o column decoder i/o1 we# input data control row decoder oe# cs# cs cs lb# ub# i/o16 i/o9 i/o8 . . . . . . a14 a13 a12 a5 a6 a7 a11 a10 a3 a1 (lsb) (msb) internal voltage generator (lsb) (msb)
r1rp0416di series rev.1.00, mar.12.2004, page 4 of 12 operation table cs# oe# we# lb# ub# mode v cc current i/o1 ? ? ? ? i/o8 i/o9 ? ? ? ? i/o16 ref. cycle h standby i sb , i sb1 high-z high-z ? l h h output disable i cc high-z high-z ? l l h l l read i cc output output read cycle l l h l h lower byte read i cc output high-z read cycle l l h h l upper byte read i cc high-z output read cycle l l h h h ? i cc high-z high-z ? l l l l write i cc input input write cycle l l l h lower byte write i cc input high-z write cycle l l h l upper byte write i cc high-z input write cycle l l h h ? i cc high-z high-z ? note: h: v ih , l: v il , : v ih or v il absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ? 0.5 to +7.0 v voltage on any pin relative to v ss v t ? 0.5 * 1 to v cc + 0.5 * 2 v power dissipation p t 1.0 w operating temperature topr ? 40 to +85 c storage temperature tstg ? 55 to +125 c storage temperature under bias tbias ? 40 to +85 c notes: 1. v t (min) = ? 2.0 v for pulse width (under shoot) 6 ns. 2. v t (max) = v cc + 2.0 v for pulse width (over shoot) 6 ns.
r1rp0416di series rev.1.00, mar.12.2004, page 5 of 12 recommended dc operating conditions (ta = ? 40 to +85 c) parameter symbol min typ max unit supply voltage v cc * 3 4.5 5.0 5.5 v v ss * 4 0 0 0 v input voltage v ih 2.2 ? v cc + 0.5 * 2 v v il ? 0.5 * 1 ? 0.8 v notes: 1. v il (min) = ? 2.0 v for pulse width (under shoot) 6 ns. 2. v ih (max) = v cc + 2.0 v for pulse width (over shoot) 6 ns. 3. the supply voltage with all v cc pins must be on the same level. 4. the supply voltage with all v ss pins must be on the same level. dc characteristics (ta = ? 40 to +85 c, v cc = 5.0 v 10%, v ss = 0 v) parameter symbol min max unit test conditions input leakage current |i li | ? 2 a v in = v ss to v cc output leakage current * 1 |i lo | ? 2 a v in = v ss to v cc operating power supply current i cc ? 160 ma cs# = v il , i out = 0 ma other inputs = v ih /v il standby power supply current i sb ? 40 ma cs# = v ih , other inputs = v ih /v il i sb1 ? 5 ma v cc cs# v cc ? 0.2 v, (1) 0 v v in 0.2 v or (2) v cc v in v cc ? 0.2 v output voltage v ol ? 0.4 v i ol = 8 ma v oh 2.4 ? v i oh = ? 4 ma capacitance (ta = +25 c, f = 1.0 mhz) parameter symbol min max unit test conditions input capacitance * 1 c in ? 6 pf v in = 0 v input/output capacitance * 1 c i/o ? 8 pf v i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
r1rp0416di series rev.1.00, mar.12.2004, page 6 of 12 ac characteristics (ta = ? 40 to +85 c, v cc = 5.0 v 10%, unless otherwise noted.) test conditions ? input pulse levels: 3.0 v/0.0 v ? input rise and fall time: 3 ns ? input and output timing reference levels: 1.5 v ? output load: see figures (including scope and jig) output load (b) (for t clz , t olz , t blz , t chz , t ohz , t bhz , t whz , and t ow ) d out 255 ? 480 ? 5 v 5 pf 1.5 v 30 pf d out rl = 50 ? output load (a) zo = 50 ? read cycle r1rp0416di -2 parameter symbol min max unit notes read cycle time t rc 12 ? ns address access time t aa ? 12 ns chip select access time t acs ? 12 ns output enable to output valid t oe ? 6 ns byte select to output valid t ba ? 6 ns output hold from address change t oh 3 ? ns chip select to output in low-z t clz 3 ? ns 1 output enable to output in low-z t olz 0 ? ns 1 byte select to output in low-z t blz 0 ? ns 1 chip deselect to output in high-z t chz ? 6 ns 1 output disable to output in high-z t ohz ? 6 ns 1 byte deselect to output in high-z t bhz ? 6 ns 1
r1rp0416di series rev.1.00, mar.12.2004, page 7 of 12 write cycle r1rp0416di -2 parameter symbol min max unit notes write cycle time t wc 12 ? ns address valid to end of write t aw 8 ? ns chip select to end of write t cw 8 ? ns 8 write pulse width t wp 8 ? ns 7 byte select to end of write t bw 8 ? ns address setup time t as 0 ? ns 5 write recovery time t wr 0 ? ns 6 data to write time overlap t dw 6 ? ns data hold from write time t dh 0 ? ns write disable to output in low-z t ow 3 ? ns 1 output disable to output in high-z t ohz ? 6 ns 1 write enable to output in high-z t whz ? 6 ns 1 notes: 1. transition is measured 200 mv from steady voltage with output load (b). this parameter is sampled and not 100% tested. 2. if the cs# or lb# or ub# low transition occurs simultaneously with the we# low transition or after the we# transition, output remains a high impedance state. 3. we# and/or cs# must be high during address transition time. 4. if cs#, oe#, lb# and ub# are low during this period, i/o pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 5. t as is measured from the latest address transition to the latest of cs#, we#, lb# or ub# going low. 6. t wr is measured from the earliest of cs#, we#, lb# or ub# going high to the first address transition. 7. a write occurs during the overlap of a low cs#, a low we# and a low lb# or a low ub# (t wp ). a write begins at the latest transition among cs# going low, we# going low and lb# going low or ub# going low. a write ends at the earliest transition among cs# going high, we# going high and lb# going high or ub# going high. 8. t cw is measured from the later of cs# going low to the end of write.
r1rp0416di series rev.1.00, mar.12.2004, page 8 of 12 timing waveforms read timing waveform (1) (we# = v ih ) t aa t acs t oe t ba t blz t olz t clz t oh t chz t ohz t bhz t rc address valid address valid data d out cs# oe# lb#, ub# high impedance * 1 * 1 * 1 * 1 * 1 * 1 * 4 * 4
r1rp0416di series rev.1.00, mar.12.2004, page 9 of 12 read timing waveform (2) (we# = v ih , lb# = v il , ub# = v il ) t aa t acs t rc t oe t clz valid data address cs# d out valid address high impedance t ohz oe# t oh t chz t olz * 1 * 1 * 1 * 1 * 4 * 4
r1rp0416di series rev.1.00, mar.12.2004, page 10 of 12 write timing waveform (1) (we# controlled) address we# * 3 t wc t aw t as t wr t wp t whz t olz t ow t ohz t cw t bw t dh t dw valid address valid data cs# * 3 oe# lb#, ub# d out d in high impedance * 2
r1rp0416di series rev.1.00, mar.12.2004, page 11 of 12 write timing waveform (2) (cs# controlled) address cs# * 3 t wc t aw t as t wr t wp t whz t olz t ow t ohz t cw t bw t dh t dw valid address valid data we# * 3 oe# lb#, ub# d out d in high impedance * 2 * 4
r1rp0416di series rev.1.00, mar.12.2004, page 12 of 12 write timing waveform (3) (lb#, ub# controlled, oe# = v ih ) address d in -ub (d in -lb) d in -lb (d in -ub) d out high impedance valid address t dw t dh t cw t as t bw t wp t wc t wr t aw we# * 3 cs# * 3 ub# (lb#) lb# (ub#) t bw valid data t dw t dh valid data
revision history r1rp0416di series data sheet contents of modification rev. date page description 0.01 sep. 30, 2003 ? initial issue 1.00 mar.12.2004 ? deletion of preliminary
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